Time: M, W 12:00 - 12:50 (lecture); M 14:30 - 17:20 (lab)

Location: Lecture: CLARK204; Lab: ENG288

Description

Digital system building blocks, data path and control units, register transfer level (RTL) design of digital systems, Verilog hardware description language (HDL) for design and verification, contemporary design flow and methodology, lab experiments using industry standard EDA tools and field programmable gate array (FPGA) devices.

Lab - EDA tools, digital hardware development flow, hands-on design, verification and FPGA implementation of functional blocks and complete systems.